Development and Comprehensive Evaluation of Closed-Loop Order Release Control Policies in Semiconductor Wafer Fabrication
Open Oral Presentation

Development and Comprehensive Evaluation of Closed-Loop Order Release Control Policies in Semiconductor Wafer Fabrication

Mr. Ragupathi T

Development and Comprehensive Evaluation of Closed-Loop Order Release Control Policies in Semiconductor Wafer Fabrication
Presenter

Presenter

Mr. Ragupathi T

PhD Research Scholar

Department of Management Studies, IISc

Date

Date

21 April 2026

16:30

Venue

Venue

Seminar Hall, Department of Management Studies, IISc, Bengaluru

Research Supervisor

Research Supervisor

Dr. M. Mathirajan, Professor, Dept. of Management Studies, IISc

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Abstract

Wafer fabrication is the most complex and capital-intensive stage of semiconductor manufacturing, characterised by re-entrant flows, diverse equipment types, batch and discrete processors, sequence-dependent setups, machine failures, and high variability. This research develops and evaluates new Closed-Loop Order Release Control (CL-ORC) policies that regulate system workload, control WIP, and ensure reliable due-date performance. Three newly proposed CL-ORC policies are empirically validated against 17 existing policies using due date-based performance measures, and shown to offer actionable insights for improving due-date performance in wafer fabrication environments.

About the Presenter

PhD research scholar at the Department of Management Studies, IISc, working on production planning and control in semiconductor manufacturing.

Additional Information

This is a PhD thesis open oral presentation. All faculty and students are welcome to attend.

Open oral presentation on closed-loop order release control policies integrated with due date-based dispatching rules to improve performance in semiconductor wafer fabrication.

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