Development and Comprehensive Evaluation of Closed-Loop Order Release Control Policies in Semiconductor Wafer Fabrication

Abstract

Wafer fabrication is the most complex and capital-intensive stage of semiconductor manufacturing, characterised by re-entrant flows, diverse equipment types, batch and discrete processors, sequence-dependent setups, machine failures, and high variability. In such environments, Closed-Loop Order Release Control (CL-ORC) policies play a crucial role in regulating system workload, controlling WIP, and ensuring reliable due-date performance. Although several studies have examined various CL-ORC policies, the literature still reveals major gaps: (i) the need to develop new CL-ORC policies that build on the strengths and address the weaknesses of existing policies. (ii) it appears that there is no comprehensive evaluation of all existing CL-ORC policies using due date-based performance measures, and (iii) very limited research on integrating CL-ORC policies with due date-based dispatching rules (DDRs) applied at bottleneck workstation with due date-based performance measures.To address these research gaps, this study first conducts an extensive analysis of all the existing 17 CL-ORC policies and subsequently proposes three new CL-ORC policies: Workload Control on Layers (WCL), Total Workload Regulating 1 (TWR-1), and TWR-2. A detailed simulation model, based on the Intel Mini-Fab that incorporates realistic wafer-fab characteristics such as re-entrant product flows, batch processing, sequence-dependent setups, breakdowns, and operator requirements, is developed using Arena Simulation Software for a comprehensive evaluation of all 20 (17 existing and 3 newly proposed) CL-ORC policies using due-date performance measures. Accordingly, the simulation experiment is carried out to evaluate the performance of all 20 CL-ORC policies using (a) three due date-based performance measures: Total Weighted Earliness/Lateness (TWE/L), Total Weighted Tardiness (TWT), and On-Time Delivery (OTD) rate independently; and (b) Weighted Performance Score (WPS) - which is based on combining of each the 3 performance measures: TWE/L, TWT and OTD rate with the computed priority weights obtained for each of the 3 performance measures using the Analytic Network Process (ANP). The simulation results obtained indicate that the performance of CL-ORC policies varies with respect to each of the due date-based performance measures considered in this study. However, the newly proposed CL-ORC policy: WCL policy outperforms all other policies with respect to the performance measures: TWT and OTD rate, while the existing CL-ORC policy: WR policy performs better for the performance measure: TWE/L. When the performance was assessed using WPS (that is combined effect of all the three due date-based performance measures considered in this study), the newly proposed CL-ORC policy: WCL policy emerges as the best-performing overall followed by the other two newly proposed policies TWR-1 and TWR-2. Recognising the critical impact of dispatching rules (DR) in semiconductor manufacturing, many studies integrated the ORC polices with Completion time-based DR (CDR) applied in the bottleneck workstation: Lithography (LG) in wafer fabrication. However, the analysis of the literature revealed that there is no study reported considering Due-date based DR (DDR) applied in bottleneck workstation: LG and integrated with ORC policies in wafer fabrication. Considering this literature gap and the importance of due date based performance measure in wafer fabrication, this study further investigates the integration of each of the 20 CL-ORC policies with each of the 10 DDRs (which are identified as frequently used DDRs in semiconductor manufacturing) applied at bottleneck workstations: LG and Diffusion Furnace (DF) with 3 scenarios: each of the DDR applied at (i) LG only, (ii) DF only, and (iii) LG and DF simultaneously. Based on the simulation experiments and the analysis of the simulation results, it is observed that across all scenarios, the newly proposed policy; WCL policy consistently demonstrates superior performance along with DDRs: ATC-Monch applied at LG, CR at applied DF, and ATC-Monch at applied LG and CR at applied DF.Overall, this study empirically proved that the newly proposed 3 CL-ORC policies are efficient in comparison with existing 17 CL-ORC polices considering due date-based performance measures considered in this study and offers actionable insights for improving due-date performance in wafer fabrication environments.